Memory barrier pairing

When implementing low-level synchronization mechanisms in multi-threaded code, ensure that memory barriers are correctly paired between reader and writer operations. For each read barrier, implement a corresponding write barrier to maintain memory consistency and prevent race conditions.

For example, in ARM64 assembly:

// Read side
dmb ishld   // Data memory barrier for load operations

// Write side (corresponding barrier needed)
dmb ishst   // Data memory barrier for store operations

Consider whether specialized atomic instructions (like ldar for loads or stlr for stores) might provide the same memory ordering guarantees with potentially better performance in specific scenarios. However, ensure these are implemented at the correct locations in the code to properly maintain the synchronization semantics.